Design and implementation of DDA architecture for FIR Filters

Traditionally, direct implementation of a K-tap FIR filter requires K multiply-and-accumulate (MAC) blocks, which are expensive to implement in FPGA due to logic complexity and resource usage. To resolve this issue, we first present DA, which is a architecture without multiplier. This paper implements the DA architecture. This architecture is applicable to only one type of filter Coefficients i.e., fixed filter coefficient. In case if we want to operate on variable filter coefficients we have been using Dynamic Distributed Arithmetic (DDA) Architecture. In this we are providing the flexibility to operate on variable filter coefficients. Here also compare DA(Distributed Arithmetic),D-DA(DecomposedDistributed Arithmetic),DDA(Dynamic Distributed Arithmetic) by using of XILINX ISE 9.1.i tool, for simulation and synthesis, dumping on sparton-3E FPGA. Keywords– Distributed Arithmetic; FIR; Decomposed DA; dynamic DA.